{"id":263,"date":"2026-04-01T12:39:15","date_gmt":"2026-04-01T12:39:15","guid":{"rendered":"https:\/\/straehl-engineering.ch\/?page_id=263"},"modified":"2026-04-01T12:48:11","modified_gmt":"2026-04-01T12:48:11","slug":"keywords","status":"publish","type":"page","link":"https:\/\/straehl-engineering.ch\/?page_id=263","title":{"rendered":"Keywords"},"content":{"rendered":"\n<p>Firmware, embedded, software, hardware, VT220 terminal.<\/p>\n\n\n\n<p>BareMetal. HDLC stack (OSI Layer1-Layer3) (PP, PMP). EmBOS, Enea, FreeRTOS, VxWorks, WindRiver, Cortex-CMSIS, BareMetal mit selbst entwickeltem Task-Manager<\/p>\n\n\n\n<p>I2C, SPI, CAN, OpenCAN, CAN overFiberOptic, DMA, IoT, WLAN, HDLC, TCP-IP, TFTP.Eclipse, VScode, Espressif IDE, Keil, MicrochipLAB,<br>STM32CubeIDE, Rhapsody.Design &amp; Analysis,<\/p>\n\n\n\n<p>LTspice<\/p>\n\n\n\n<p>Altium designer<\/p>\n\n\n\n<p>Eclipse, VScode, Espressif IDE, Keil, MicrochipLAB,<br>STM32CubeIDE, GnuTools, IAR, Renesas E2-Studio, SVN,<br>GIT, Trac, Polarion, Jira, Confluence, PTC, Codebeamer, Rhapsody, Enterprise Architect.<\/p>\n\n\n\n<p>ARM Cortex, ESP32, STM32, NXP, CMSIS, Microchip-PIC. Motorola<\/p>\n\n\n\n<p>SVN, GIT<\/p>\n\n\n\n<p>Eclipse, VScode, Espressif IDE, Keil, MicrochipLAB,<br>STM32CubeIDE, GnuTools, IAR, Renesas E2-Studio, SVN,<br>GIT, Trac, Polarion, Jira, Confluence, PTC, Codebeamer, Rhapsody, Enterprise Architect.<\/p>\n\n\n\n<p>Embedded Software Entwicklung<br>\u2022 Unit- \/ Integration-Testing<br>\u2022 REQ \/ SPEC Engineering<br>\u2022 Analyse, Design, Architektur<br>\u2022 Coaching, PL\/QM\/PM\/PO-Support<\/p>\n\n\n\n<p><\/p>\n\n\n\n<p><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Projektauftrag f\u00fcr die gesamte Embedded-FW L\u00f6sung<\/li>\n\n\n\n<li>Teile des Projektes, SystemStart, Konfiguration, Monitoring..<\/li>\n\n\n\n<li>Aufsetzen und Impl. aller ben\u00f6tigten Tasks<\/li>\n\n\n\n<li>HW Prototype Optimierung<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Firmware, embedded, software, hardware, VT220 terminal. BareMetal. HDLC stack (OSI Layer1-Layer3) (PP, PMP). EmBOS, Enea, FreeRTOS, VxWorks, WindRiver, Cortex-CMSIS, BareMetal mit selbst entwickeltem Task-Manager I2C, SPI, CAN, OpenCAN, CAN overFiberOptic, DMA, IoT, WLAN, HDLC, TCP-IP, TFTP.Eclipse, VScode, Espressif IDE, Keil, MicrochipLAB,STM32CubeIDE, Rhapsody.Design &amp; Analysis, LTspice Altium designer Eclipse, VScode, Espressif IDE, Keil, MicrochipLAB,STM32CubeIDE, GnuTools, IAR, [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-263","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=\/wp\/v2\/pages\/263","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=263"}],"version-history":[{"count":2,"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=\/wp\/v2\/pages\/263\/revisions"}],"predecessor-version":[{"id":266,"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=\/wp\/v2\/pages\/263\/revisions\/266"}],"wp:attachment":[{"href":"https:\/\/straehl-engineering.ch\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=263"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}